The present invention relates to a semiconductor storage unit. More specifically, the present invention concerns a technology effectively applied to a nonvolatile semiconductor storage unit such as flash memory using a technology called a single-end sensing system, i.e., a technique which provides a sense latch circuit at one end of a bit line and uses the sense latch circuit to detect voltages on the bit line corresponding to a threshold voltage of a memory cell.
According to the inventors' investigation, the following technology is available for the flash memory as an example of the nonvolatile semiconductor storage unit.
For example, the flash memory uses a memory cell that comprises a nonvolatile storage element having a control gate and a floating gate. One transistor can constitute a memory cell. Such flash memory adopts a so-called “multivalued” flash memory concept to store two bits or more of data in one memory cell for increasing the storage capacity. The multivalued flash memory controls the amount of electric charge supplied to the floating gate to gradually change a threshold voltage. It is possible to store a plurality of bits of information corresponding to each threshold voltage.
The above-mentioned flash memory increases its chip size as the storage capacity increases. It is also necessary to prevent the chip size from increasing. In consideration for the chip size, for example, there are many restrictions on an area of a memory array comprising a plurality of memory cells displaced at intersecting points between word lines and bit lines in a matrix. A particular attention needs to be placed on an area of a Y access circuit and the like in the memory array. The Y access circuit for the flash memory is configured using technologies called the open bit sensing system and the single-end sensing system, for example.
The following documents are examples that describe technologies concerning the flash memory using the single-end sensing system.                1999 IEEE International Solid-State Circuits Conference, MP6.6:A130 mm2 256 Mb NAND Flash with Shallow Trench Isolation Technology        1995 IEEE International Solid-State Circuits Conference, TA7.5:A3.3V32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme        1995 IEEE International Solid-State Circuits Conference, TA7.6:A 35 ns-Cycle-Time 3.3V-Only 32 Mb NAND Flash EEPROM        
The following is made clear after the inventors examined the technologies using the open bit sensing system and the single-end sensing system concerning the Y access circuit for the flash memory as mentioned above.
The open bit sensing system is configured to connect two global bit lines to both ends of the sense latch circuit. As a first presupposed technology of the present invention, the open bit sensing system will be described with reference to a circuit diagram in FIG. 9 showing a Y access circuit. In addition, FIG. 10 is used to describe sense operations of the open bit sensing system (a) and the single-end sensing system (b) as a second presupposed technology of the present invention.
As shown in FIG. 9, the Y access circuit in the open bit sensing system comprises a sense latch circuit 101 and the other circuits in pairs connected to a global bit line G-BL extending from both ends of the sense latch circuit 101. The circuits in pairs include: global bit line precharge circuits 111 and 121; global bit line discharge circuits 112 and 122; global bit line selective precharge circuits 113 and 123; transfer circuits 114 and 124; sense latch node control circuits 115 and 125; all-determination circuits 116 and 126; and Y-selection switch circuits 117 and 127.
The sense latch circuit 101 comprises PMOSFETs Q51 and Q52 and NMOSFETs Q53 and Q54. The sense latch circuit 101 senses a threshold state of the memory cell and latches data after the sense operation.
The global bit line precharge circuits 111 and 121 comprise NMOSFETs Q61 and Q71 and precharge the global bit line G-BL at a time.
The global bit line discharge circuits 112 and 122 comprise NMOSFETs Q62 and Q72 and discharge the global bit line G-BL at a time.
The global bit line selective precharge circuits 113 and 123 comprise NMOSFETs Q63, Q64, Q73, and Q74 and selectively precharge the global bit line G-BL based on a given unit.
The transfer circuits 114 and 124 comprise NMOSFETs Q65 and Q75 and make connection or disconnection between the sense latch circuit 101 and the global bit line G-BL.
The sense latch node control circuits 115 and 125 comprise NMOSFETs Q66 and Q76 and charge or discharge nodes in the sense latch circuit 101.
The all-determination circuits 116 and 126 comprise NMOSFETs Q67 and Q77 and determine latch data in the sense latch circuit 101.
The Y-selection switch circuits 117 and 127 comprise NMOSFETs Q68 and Q78 and function as switches to input and output data between the sense latch circuit 101 and a common input/output line.
When the open bit sensing system is used as shown in FIG. 10(a), the memory cell MC is connected to one global bit line G-BL (left). The global bit line G-BL is set to a voltage corresponding to the memory threshold voltage. A reference voltage is applied to the other global bit line G-BL (right) The open bit sensing system uses a relatively large capacity for the global bit line G-BL. Both global bit lines G-BL use almost the same capacity, enabling stable sense operations.
On the other hand, the single-end sensing system is configured to lay out the sense latch circuit at one end of the global bit line G-BL. The single-end sensing system aims at reducing the area, i.e., decreasing the number of elements. When the single-end sensing system is used as shown in FIG. 10(b), only one side of the sense latch circuit is connected to the global bit line G-BL. The capacity of the reference side decreases approximately one sixth of that of the sense side. The single-end sensing system performs sense operations with a large capacity difference between both sides of the sense latch circuit, causing a problem of miss sensing.
The above-mentioned open bit sensing system uses many elements for supplementary circuits to control two global bit lines G-BL, facing a problem of reducing the layout area by decreasing the number of elements. For example, the above-mentioned Y access circuit in FIG. 9 requires:
4 elements for the sense latch circuit 101;
1×2=2 elements for the global bit line precharge circuits 111 and 121;
1×2=2 elements for the global bit line discharge circuits 112 and 122;
2×2=4 elements for the global bit line selective precharge circuits 113 and 123;
1×2=2 elements for the transfer circuits 114 and 124;
1×2=2 elements for the sense latch node control circuits 115 and 125;
1×2=2 elements for the all-determination circuits 116 and 126; and
1×2=2 elements for the Y-selection switch circuits 117 and 127.
It is therefore an object of the present invention to provide a nonvolatile semiconductor storage unit capable of preventing erratic sense operations in a sense latch circuit by using the single-end sensing system capable of reducing an area (decreasing the number of elements).